Method to reduce midrange resonance during operation of a multi-phase step motor

ABSTRACT

The frequency of the pulse width modulator within a step motor control circuit is increased above a base frequency under defined conditions to enable more accurate construction of the phase current waveform for reducing mid-range resonance. The PWM frequency is stepped between frequencies by a fixed amount above the base frequency, to reduce the excitation of system harmonics and prevent step motor operational instability.

BACKGROUND OF THE INVENTION

Step motor systems sometimes experience an operational instability knownas “mid-freguency” or “mid-range” resonance.

This instability which often causes loss of motor torque and leads tomotor stall, is caused by an interaction between the step motor drive,power supply and step motor load. When observing the step motor phasecurrent, the shape and magnitude thereof are unstable.

Previous methods to prevent mid-range resonance include modifications tothe power supply, connection of choke coils to the step motor andcircuits designed to produce signals indicative of error. The drawbacksto these methods lie in the extra complexity involved. These methodsalso may need to be tuned to the specific system of step motor, stepmotor drive, power supply and load

U.S. Pat. No. 5,264,770 entitled “Stepper Motor Driver Circuit”; “U.S.Pat. No. 4,675,590 entitled “Stepping Motor Driver with Mid-frequencyStability Control” and U.S. Pat. No. 4,319,175 entitled “StabilizedStepping-motor System “ each describe early circuits relating to stepmotor controllers.

One purpose of the present invention is to reduce midrange resonance ina multiphase step motor for improved step motor performance.

SUMMARY OF THE INVENTION

The frequency of the pulse width modulator, “PWM”, within a step motorcontrol circuit is increased above a base frequency under definedconditions to enable more accurate construction of the phase currentwaveform for reducing mid-range resonance. The PWM frequency is steppedbetween frequencies by a fixed amount above the base frequency, toreduce the excitation of system harmonics.

The PWM is synchronized to the incoming step input once per cycle toprevent the motor step clock from ‘beating’ against the PWM frequency.Improved current control leads to less phase current lag resulting ingreater stability.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic representation of the step motor control circuitin accordance with the invention;

FIG. 2 is a diagrammatic representation of the signal waveforms withinthe circuit of FIG. 1 showing the PWM_OSC frequency change;

FIG. 3 is a diagrammatic representation of the signal waveforms showingthe synchronization of the PWM oscillator within the control circuit ofFIG. 1; and

FIG. 4 is a flow chart diagram depicting the logic for changing thePWM-OSC frequency in accordance with the teachings of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The SET POINT GENERATOR 11, within the step motor control circuit 10 ofFIG. 1, creates a FRONT_SLOPE signal 24 (FIG. 2) on conductor 12 and aSIGN signal 29 (FIG. 3) on conductor 13 in response to the STEP signalinput on conductor 14. The FRONT_SLOPE signal on conductor 12 occurswhen the SIGN signal is present on conductor 13 and the STEP signal onconductor 14 causes the step motor phase current to increase for onequarter of a cycle.

These signals connect to and influence the operation of a PWMOSCILLATOR, “PWM_OSC” 15 that creates the PWM_OSC signal 26 (FIG. 2) onconductor 16. These signals, along with others (not shown), are inputtedto the BRIDGE CONTROL LOGIC, “LOGIC ”17. The PWM_OSC signal on conductor16 along with others (not shown) direct the operation of the LOGIC, 17.The LOGIC 17, through conductors 18-21 operate the H BRIDGE 22 thatcontrols the flow of step motor phase current through MOTOR PHASE COIL,“COIL” 23. Although one COIL 23 is shown, the other COILS (not shown)are connected in a similar manner.

Referring now to FIGS. 1-3, the PWM_OSC 15 creates the PWM_OSC signal 26at frequencies that range between a low or base frequency up to aspecified maximum frequency. The PWM_OSC 15 starts at the base frequencyand increases the frequency, if required, to maintain a specifiedminimum number of edges 27 of the PWM_OSC signal 26 during theFRONT_SLOPE period until the specified maximum frequency is reached.Having a minimum number of edges enables more accurate construction ofthe phase current for reducing mid-range resonance.

The PWM-OSC 15 counts the number of PWM_OSC edges 27 during the occasionof the FRONT_SLOPE signal 24. If there are fewer than the minimum numberof edges specified and the maximum frequency has not been reached, thePWM_OSC frequency is increased by a fixed amount when the FRONT_SLOPEsignal ends as indicated at 25. If the number of edges 27 of the PWM_OSCsignal 26 is greater than or equal to the number specified during theoccasion of the FRONT_SLOPE signal 24, the PWM_OSC frequency isdecreased by a fixed amount when the FRONT_SLOPE signal ends asindicated at 25.

When the FRONT_SLOPE signal 24 is stable or changing slowly and the PWMfrequency is above the base, the PWM frequency will repetitively stepbetween two frequencies. This step between frequencies occurs when thefrequency, in one cycle, is increased creating more PWM_OSC edges 27. Inthe next cycle, (not shown) the number of edges 27 of the PWM_OSC signal26 will be greater than or equal to the minimum number of edgesspecified, therefore causing the frequency to decrease. The steppingbetween frequencies reduces the excitation of system harmonics, therebyreducing mid-range resonance.

In the case where the signal period of the FRONT_SLOPE signal 24 isdecreasing rapidly, the PWM-OSC 15 will increase the frequency by afixed amount each cycle until the maximum frequency is reached or theperiod of the FRONT_SLOPE signal 24 becomes stable, whichever occursfirst.

In the case where the period of the FRONT_SLOPE signal 24 is increasingrapidly and the frequency of the PWM_OSC signal 26 is above the base,the PWM-OSC 15 will decrease the frequency by a fixed amount each cycleuntil the base frequency is reached or the period of the FRONT_SLOPEsignal becomes stable, whichever occurs first.

If at the end of a cycle, the frequency of the PWM_OSC signal 26 isincreased to the maximum, the frequency of the PWM_OSC signal will bedecreased at the end of the next cycle, even though there may be fewerthan the number of specified edges 27 of the PWM_OSC signal 26. On thefollowing cycles, the PWM_OSC frequency is increased back to the maximumfrequency. This continues the beneficial stepping between PWM_OSCfrequencies even at the maximum frequency limit.

It is to be noted that the counting of PWM_OSC edges 27 could beperformed during any portion of the motor operating cycle.

The phase current 28 transitions through zero, as indicated in phantom,twice per cycle, although only one cycle is shown in FIG. 3. At one ofthe transitions, indicated by the SIGN signal 29 on conductor 13, thePWM oscillator 15 resets its frequency generator as indicated 30 therebysynchronizing the PWM oscillator to the phase current. The phase currentchanges in response to a step input, such that the PWM oscillator issynchronized once per sine cycle to the incoming step input. Thissynchronization prevents the frequency of the step input from “beating”against the PWM oscillator frequency, reducing the potential of midrangeresonance. It is to be noted the synchronization could occur at anypoint within the sine cycle.

A flow chart diagram 31 is depicted in FIG. 4 for the control of the PWMoscillator logic 15 of FIG. 1.

A count is made of the number of PWM-OSC edges during FRONT-SLOPE (32)and a determination is made as to whether the number of PWM-OSC edges isless than a predetermined minimum (33). If the number of PWM-OSC edgesis less than a predetermined minimum, a determination is made as towhether the PWM-OSC frequency is at a predetermined maximum (34). If thePWM-OSC is not at a predetermined maximum, the PWM-OSC frequency isincreased (36) and the number of PWM-OSC edges during FRONT-SLOPE isre-counted (32).

If the PWM-OSC frequency is at a predetermined maximum, the PWM-OSCfrequency is decreased (37) and the number of PWM-OSC edges duringFRONT-SLOPE is re-counted (32).

If the number of PWM-OSC edges is not less than a predetermined minimum,a determination is made as to whether the PWM-OSC frequency is above abase value (35) and if not, the number of PWM-OSC edges duringFRONT-SLOPE is re-counted (32). If the PWM-OSC frequency is above a basevalue, the PWM-OSC frequency is decreased (37) and the number of PWM-OSCedges during FRONT-SLOPE is re-counted (32).

It has herein been shown that careful control of the PWM-OSC frequencyto construct the phase current waveform in a step motor reducesmid-range resonance and helps to eliminate motor stall.

1. A method for reducing midrange resonance in a step motor systemcomprising: determining a present operating frequency of a pwmoscillator within a motor controller circuit; comparing said presentoperating frequency to a predetermined pwm oscillator base frequency;and increasing said present pwm oscillator operating frequency abovesaid predetermined pwm oscillator base frequency when said presentoperating frequency is below said predetermined pwm oscillator basefrequency and decreasing said present pwm oscillator operating frequencywhen said present pwm oscillator operating frequency is above basefrequency to thereby improve creation of phase current within said motorcontroller circuit;
 2. (canceled)
 3. The method of claim 1 wherein saidpresent pwm oscillator operating frequency defines a signal having afront slope.
 4. The method of claim 3 wherein said present operatingfrequency is determined upon occurrence of said front slope signal. 5.The method of claim 3 wherein said pwm oscillator frequency is adjustedupon cessation of said front slope signal.
 6. A method for reducingmidrange resonance in a step motor system comprising: synchronizing apwm oscillator signal within a motor controller circuit to a step motoroperating current waveform generated by said controller circuit tothereby prevent interaction between an input signal to said motorcontroller circuit and said pwm oscillator signal thereby reducingmidrange step motor operating current resonance.
 7. A circuit forconstructing a phase current waveform in a step motor comprising: a setpoint generator connecting with a pwm oscillator for providingfront-slope and sign data to said pwm oscillator; a bridge control logicconnecting with said pwm oscillator and an H bridge, said bridge controllogic-arranged for providing a step motor operating current defining anoperating current waveform, for connecting a pwm signal with said stepmotor bridge control logic, for determining a pwm frequency during aportion of said operating current waveform, for decreasing said pwmfrequency when said pwm frequency exceeds a predetermined value, forincreasing said pwm frequency when said frequency is less than saidpredetermined value, and synchronizing said pulse width modulator tosaid step motor operating current thereby controlling step motor phasecurrent through said H bridge to a step motor coil to thereby reduceoccurrence of system harmonics of said step motor phase current. 8.(canceled)